| |
Launched in March 1999 the initial version of the Pentium III Xeon, Tanner, saw the same revisions over the Drake core of the Pentium II Xeon (revised L1 cache controller and SSE instructions). It maintained the off-die L2 cache running at full core speed in either 512KiB, 1MiB or 2MiB quantities.
This was followed by Cascades in October 1999. Essentially nothing more than a Coppermine core Pentium 3 in a Slot 2 package, with the same 256KiB L2 cache and 133MHz front side bus as its desktop equivalent.
Later versions of Cascades with 1MiB and 2MiB L2 cache on-die were released in May 2000, with a clock speed of 700MHz. The 256KiB L2 version scaled up to 1GHz.
| Derivative |
Interface |
FSB Frequency |
Clock Frequencies (MHz) |
Technologies |
| Tanner 512KiB |
Slot 2 |
100MHz |
500, 550 |
250nm process, MMX and SSE SIMD Instruction set, full speed L2 cache |
| Tanner 1MiB |
| Tanner 2MiB |
| Cascades 256KiB |
133MHz |
600, 667, 733, 800, 866, 933, 1000 |
180nm process, MMX and SSE SIMD Instruction set, on-die L2 cache |
| Cascades 1MiB |
100MHz |
700 |
| Cascades 2MiB |
There are presently no Pentium III Xeon's in the CPU archive.
|
|