Celeron™

The Celeron was introduced as a low end part in April 1998 to replace the now defunct Pentium MMX in the value segment.
The initial derivative, the Covington core was effectively a Deschutes core Pentium II with the expensive L2 cache chips removed from the package but despite a higher clock speed than the Pentium MMX the lack of L2 cache crippled it and it quickly developed a poor reputation.

To stem the tide of bad press and lackluster sales the Mendocino core quickly followed it up and was launched on the August 24th of the same year at speeds of 300 (called the 300A to avoid confusion with the older, cache less part) and 333MHz.
The big change with the Mendocino was that it saw 128KiB of L2 integrated into the die, in a similar way to mobile Pentium II 'Dixon' processor. This saw performance of the 300MHz chip double in some benchmarks compared to the equivalent Covington and suddenly the Celeron became a performance bargain.
Since it was integrated into the die the cache ran at full speed instead of half speed for the on-package cache of a Pentium II.
The Socket 370 package was also introduced to reduce CPU cost by doing away with the PCB rendered redundant by the removal of the off-die L2 cache chips.
The integration of cache into the die also meant that overclocking was far easier as systems were not limited by the rating of the L2 cache chips, it was not uncommon to see Celeron 300A's reaching 450MHz by simply setting the jumper on a 440BX motherboard to use a 100MHz front side bus.
ABit's BP6 also helped bring multi-processing to the masses, able to take a pair of Socket 370 Celeron's and run them overclocked to create a very powerful system for less than the cost a single Pentium II.
The Mendocino eventually scaled to 533MHz but the lower clock speed chips remained popular with enthusiasts as there low multipliers (not to mention low price) allowed for higher front side bus speeds when overclocking.

With the release of the Coppermine core Pentium III, and its transition to a 180nm process technology complete with on-die L2 cache the introduction of Coppermine-128 in March 2000 was an obvious move.
This saw the L2 cache size of the Coppermine slashed in half to 128KiB but in reality these were simply full blown Coppermine cores with half the cache disabled, possibly due to manufacturing defects or simply to meet demand. This meant the Celeron also gained SSE instructions.
Initially the Coppermine-128 was available only on a 66MHz front side bus to maintain a performance gap to the Pentium III, but in January 2001 100MHz FSB models were made available and speeds gradually were scaled up to 1.1GHz.

Finally the Tualatin core Celeron was released as a rather low key affair. This was effectively just a 100MHz FSB version of the standard Pentium III Tualatin core and sold in parallel to the Pentium 4 based Celeron. A fairly rare chip but popular with notebook users due to the 130nm process and the P6 architectures low power consumption compared to Netburst.

Archived Celeron's®

Matched Pair of Celeron 400 Socket 370's

Bought off of eBay. Complete set, matched pair of Celeron 400's, ABit BP6 motherboard and memory.
Fully working.