Dual Core Xeon®

Paxville

The first Dual Core Xeon, Paxville, was introduced on October 10th, 2005, amidst increased competition in the server and workstation market.
It was effectively a pair of Irwindale cores side-by-side in a single die, similar to the Smithfield core Pentium D and based on the same 90nm process, but with 2MB L2 cache per core as opposed to 1MB, and running at 2.8GHz on an 800MHz front side bus (4 x 200MHz).

Unfortunately under most work loads performance was not sparkling.
Paxville CPU's sat in the same socket, and shared the same chipset's, as the single core 64-bit Xeon's which meant that all four cores had to share the same single front side bus to the Memory Controller Hub, which itself only had a mere dual channel Registered DDR2-400. With two cores this was already becoming a performance limiting factor, and even a Pentium D running the 945 chipset with DDR2-533 had more memory bandwidth. Once you doubled that then you were effectively giving each core half the front side bus bandwidth of a first generation Pentium 4 and if the work load couldn't be fitted into cache performance could be abysmal. A TDP of 135w was a little on the toasty side too.

The Paxville MP, known as the Dual Core Xeon 70xx-series, followed in December of the same year and came in more variants. Bizarrely despite the fact that like its two socket counterpart all the processors in a Xeon MP system at this point all shared a single front side bus, and therefore the bandwidth available was being spread even more thinly, the 2.67 (667MHz FSB) and 2.8GHz (800MHz FSB) both had there L2 cache slashed to 1MiB per core, while the 3GHz (667 or 800MHz FSB) got the full 2MiB along with the dubious honor of, at a 165w TDP, being the most power hungry processors Intel have ever produced.

Dempsey

Dempsey, the second generation of Dual Core Xeon (50xx-series) launched on 23rd May 2006 and brought along with it a raft of changes to the underlying architecture of the Xeon platform.
Out went the E7000-series chipset's replaced by the 5000x and with it came Dual Independent Bus's (a front side bus to each CPU), Quad Channel Fully-Buffered DDR2-667 (allowing for far greater memory bandwidth, easier trace routing on the motherboard and more memory slots), an LGA socket, and various new RAS functionality normally reserved for higher end quad socket systems.
There were some issues (power consumption of the FB-DIMM's for example) but in general it was a big step forward.

The Dempsey CPU itself however was less revolutionary. Effectively little more than an SMP capable Presler cored Pentium Extreme Edition it still represented a big step forward compared to Paxville with the 65nm process allowing for higher clock speeds and (slightly) lower power consumption with a TDP of 95w for the 2.67, 2.8 and 3.2GHz 'medium voltage' parts and 130w for the standard 3.2GHz and 3.73GHz models. Front side bus speeds were 667MHz (4 x 166) for the lower speed parts and 1066MHz (4 x 266) for the higher speed parts.
Dempsey made a far more viable choice against competition than Paxville was able to, but the underlying platform got the chance to truly shine a month later with the launch of the Core Microarchitecture.

Tulsa

While two socket Xeon systems were transitioning to the Core Microarchitecture an MP equivalent was not yet ready.
With Paxville MP in desperate need of replacement but the MP's underlying architecture not getting the two socket style reinvigoration just yet a new Netburst based CPU was required that could try and work around the deficiencies of the platform beneath it. The path chosen was cache, lots and lots of cache!

Tulsa, like the low-end Paxville's, had just 1MiB of L2 cache per core, but brought between 4 and 16MiB of shared L3 cache to the party.
2MiB of this per CPU is most likely used to shadow the L2 cache of the other processor on the die to reduce cache snooping between the cores over the front side bus, with the rest being used in the traditional manner.

Tulsa exist in two main forms 71xxN's have a 667MHz front side bus, while 71xxM's have an 800MHz front side bus. Cache size increases with the clock speed, which presumably means lower clock speed parts could be made from parts with some faulty L2 cache, especially useful given the very large die size of the Tulsa core which since it has shared L3 cache could not be formed from fitting two dies to a single substrate as seen with Dempsey.

Archived Dual Core Xeon® 3.2GHz

Pre-qualification Engineering Sample. Pulled from a demo unit that was being scraped. Small typo on heatspreader - QFCIES should read QFCI ES
Working but unknown how usable. (Markings in pen on heatspreader are my own)