The Unofficial Intel CPU Archive

Celeron™

Intel Celeron Logo

The Netburst version of the Celeron was launched in May of 2002 on the Socket 478 platform. Initially all Pentium 4 systems had been tied to expensive Rambus RDRAM modules through the i850 chipset. However with the launch of the i845, supporting PC133 memory, and later the i845D with support for DDR PC2100 the cost of building a Netburst based budget system was substantially reduced and so the Celeron was moved over to the newer architecture.

What resulted was basically simply a 128KiB L2 cache version of the Willamette, and then in September 2002 higher speed grades based on the Northwood, again with 128KiB.
The change to the Northwood core saw no real speed improvement per clock as both chips shared the same design and with both capped at 128KiB there was no major differences between them. The move to 130nm did allow more chips to be produced per wafer however which reduced production costs.

A Mobile Celeron was also produced, also based off the Northwood core but with 256KiB of L2 cache. Since the mobile chips were pin compatible with desktop boards, had a TDP or 35W at 2.5GHz compared to 61W for the desktop part and 256KiB provided a large performance improvement these made an interesting choice for the enthusiast.

Derivative	Interface	FSB Frequency	Clock Frequencies (GHz)	Technologies
Willamette-128KiB	Socket 478	400MHz (4 x 100)	1.7, 1.8	180nm process, MMX, SSE and SSE2 SIMD Instructions, 128KiB on-die L2 cache
Northwood-128KiB			2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8	130nm process, MMX, SSE and SSE2 SIMD Instructions, 128KiB on-die L2 cache
Northwood-256KiB			1.4, 1.5, 1.6, 1.7, 1.8, 2.0, 2.2, 2.4, 2.5	130nm process, MMX, SSE and SSE2 SIMD Instructions, 256KiB on-die L2 cache

Archived Celeron's®

There are presently no Netburst Celeron's in the CPU archive.